/*
 * Copyright (C) Cvitek Co., Ltd. 2021-2023. All rights reserved.
 *
 * File Name: cv186x-clock.h
 * Description:
 */

#ifndef __DT_BINDINGS_CLK_CV186X_H__
#define __DT_BINDINGS_CLK_CV186X_H__

#define CV186X_CLK_FPLL		     0
#define CV186X_CLK_MPLL		     1
#define CV186X_CLK_TPLL		     2
#define CV186X_CLK_MIPIMPLL0		     3
#define CV186X_CLK_CAM0PLL		     4
#define CV186X_CLK_DISPPLL0		     5
#define CV186X_CLK_MIPIMPLL1		     6
#define CV186X_CLK_CAM1PLL		     7
#define CV186X_CLK_DISPPLL1		     8
#define CV186X_CLK_MIPIMPLL2		     9
#define CV186X_CLK_A0PLL		     10
#define CV186X_CLK_A53PLL		     11
#define CV186X_CLK_RVPLL		     12
#define CV186X_TOP_CLK_FAB0		     13
#define CV186X_TOP_CLK_FAB1		     14
#define CV186X_TOP_CLK_HSPERI		     15
#define CV186X_RTC_CLK_RTC_FAB		     16
#define CV186X_TOP_CLK_1M		     17
#define CV186X_AP_CPU_CLK		     18
#define CV186X_AP_CLK_RV0		     19
#define CV186X_AP_DBG_CLK		     20
#define CV186X_AP_SC_CLK		     21
#define CV186X_AP_BUS_CLK		     22
#define CV186X_AP_CLK_SECURITY		     23
#define CV186X_AP_CLK_HSPERI_FAB	     24
#define CV186X_AP_CLK_PERI_FAB		     25
#define CV186X_AP_CA53_PM_CLKIN	     26
#define CV186X_AP_CLK_RTC_FAB		     27
#define CV186X_AP_CLK_TOP_FAB0		     28
#define CV186X_TPU_CLK_TPU		     29
#define CV186X_TPU_CLK_TOP_FAB0	     30
#define CV186X_TPU_CLK_TC906B		     31
#define CV186X_TPU_CLK_TIMER_50M	     32
#define CV186X_TPU_CLK_GDMA		     33
#define CV186X_VD0_CLK_SRC1_VDSYS	     34
#define CV186X_VD0_CLK_SRC0_VDSYS	     35
#define CV186X_VD0_CLK_SRC2_VDSYS	     36
#define CV186X_VD0_CLK_AXI_VDSYS_0	     37
#define CV186X_VD0_CLK_AXI_VDSYS_1	     38
#define CV186X_VD0_CLK_TOP_AXI		     39
#define CV186X_VD1_CLK_SRC1_VDSYS	     40
#define CV186X_VD1_CLK_SRC0_VDSYS	     41
#define CV186X_VD1_CLK_SRC2_VDSYS	     42
#define CV186X_VD1_CLK_AXI_VDSYS_0	     43
#define CV186X_VD1_CLK_AXI_VDSYS_1	     44
#define CV186X_VD1_CLK_TOP_AXI		     45
#define CV186X_VE_CLK_SRC1_VESYS	     46
#define CV186X_VE_CLK_SRC0_VESYS	     47
#define CV186X_VE_CLK_SRC2_VESYS	     48
#define CV186X_VE_CLK_AXI_VESYS	     49
#define CV186X_VE_CLK_TOP_AXI		     50
#define CV186X_VI_CLK_X2P		     51
#define CV186X_VI_CLK_RAW_AXI		     52
#define CV186X_VI_CAM0_CLK		     53
#define CV186X_VI_CAM1_CLK		     54
#define CV186X_VI_CAM2_CLK		     55
#define CV186X_VI_CLK_SRC_VI_SYS_0	     56
#define CV186X_VI_CLK_SRC_VI_SYS_1	     57
#define CV186X_VI_CLK_SRC_VI_SYS_2	     58
#define CV186X_VI_CLK_SRC_VI_SYS_3	     59
#define CV186X_VI_CLK_SRC_VI_SYS_4	     60
#define CV186X_VI_CLK_SRC_VI_SYS_5	     61
#define CV186X_VO_CLK_RAW_AXI		     62
#define CV186X_VO_CLK_X2P		     63
#define CV186X_VO_CLK_SRC_VO_SYS_0	     64
#define CV186X_VO_CLK_SRC_VO_SYS_1	     65
#define CV186X_VO_CLK_SRC_VO_SYS_2	     66
#define CV186X_VO_CLK_SYS_DISP0	     67
#define CV186X_VO_CLK_SYS_DISP1	     68
#define CV186X_VO_CLK_RAW_DSI_TX_ESC0	     69
#define CV186X_VO_CLK_RAW_DSI_TX_ESC1	     70
#define CV186X_VO_CLK_SFR		     71
#define CV186X_VO_CLK_MIPIMPLL0	     72
#define CV186X_VO_CLK_MIPIMPLL1	     73
#define CV186X_DDR_ACLK_M2_SYS1	     74
#define CV186X_DDR_CLKI_DDRPLL_MAS_REF_SYS1 75
#define CV186X_DDR_CLKI_DDRPLL_MAS_REF_SYS2 76
#define CV186X_DDR_ACLK_M1_SYS1	     77
#define CV186X_DDR_ACLK_M1_SYS2	     78
#define CV186X_DDR_ACLK_M4_SYS1	     79
#define CV186X_DDR_ACLK_M4_SYS2	     80
#define CV186X_DDR_PCLK_CTRL_SYS1	     81
#define CV186X_DDR_PCLK_CTRL_SYS2	     82
#define CV186X_DDR_TOP_FAB_ACLK_OFFLINE     83
#define CV186X_DDR_TOP_FAB_ACLK_RLT	     84
#define CV186X_DDR_TOP_FAB_ACLK_TPU	     85
#define CV186X_DDR_TOP_FAB_ACLK_OFFLINE_M1  86
#define CV186X_DDR_TOP_FAB_ACLK_OFFLINE_M2  87
#define CV186X_DDR_TOP_FAB_ACLK_OFFLINE_M3  88
#define CV186X_DDR_TOP_FAB_ACLK_OFFLINE_M4  89
#define CV186X_DDR_TOP_FAB_ACLK_OFFLINE_M5  90
#define CV186X_DDR_TOP_FAB_ACLK_OFFLINE_M6  91
#define CV186X_DDR_TOP_FAB_ACLK_OFFLINE_M7  92
#define CV186X_DDR_TOP_FAB_ACLK_OFFLINE_M8  93
#define CV186X_DDR_TOP_FAB_ACLK_OFFLINE_M9  94
#define CV186X_DDR_TOP_FAB_ACLK_OFFLINE_M10 95
#define CV186X_DDR_TOP_FAB_ACLK_OFFLINE_M11 96
#define CV186X_DDR_TOP_FAB_ACLK_OFFLINE_M12 97
#define CV186X_DDR_TOP_FAB_PCLK_FW	     98
#define CV186X_DDR_TOP_FAB_PCLK_TOP	     99
#define CV186X_USB_CLK_TOP_USB_FAB	     100
#define CV186X_USB_TEST_PHY_CLK_480	     101
#define CV186X_USB_TEST_PHY_CLK_500	     102
#define CV186X_USB_CLK_USB_FAB		     103
#define CV186X_USB_CLK_USB_SUSPEND	     104
#define CV186X_SSPERI_ACLK_DDR		     105
#define CV186X_SSPERI_ACLK_CFG2TOP	     106
#define CV186X_SSPERI_ACLK_CFG		     107
#define CV186X_SSPERI_TEST_PHY_CLK	     108
#define CV186X_CLK_RXOOB		     109
#define CV186X_CLK_SD0			     110
#define CV186X_CLK_100K_SD0		     111
#define CV186X_CLK_SD1			     112
#define CV186X_CLK_100K_SD1		     113
#define CV186X_CLK_SD2			     114
#define CV186X_CLK_100K_SD2		     115
#define CV186X_CLK_EMMC		     116
#define CV186X_CLK_100K_EMMC		     117
#define CV186X_CLK_ETH0_TX		     118
#define CV186X_CLK_ETH1_TX		     119
#define CV186X_CLK_ETH1_REF		     120
#define CV186X_CLK_ETH0_REF		     121
#define CV186X_CLK_AXI4_ACLK		     122
#define CV186X_CLK_SPI_NAND		     123
#define CV186X_CLK_AUDSRC		     124
#define CV186X_CLK_AUD0		     125
#define CV186X_CLK_AUD1		     126
#define CV186X_CLK_AUD2		     127
#define CV186X_CLK_AUD3		     128
#define CV186X_CLK_AUD4		     129
#define CV186X_CLK_AUD5		     130
#define CV186X_CLK_AUD_DW		     131
#define CV186X_CLK_SPI			     132
#define CV186X_CLK_I2C			     133
#define CV186X_CLK_UART0		     134
#define CV186X_CLK_UART1		     135
#define CV186X_CLK_UART2		     136
#define CV186X_CLK_UART3		     137
#define CV186X_CLK_UART4		     138
#define CV186X_CLK_UART5		     139
#define CV186X_CLK_UART6		     140
#define CV186X_CLK_UART7		     141
#define CV186X_CLK_CAN			     142
#define CV186X_CLK_WDT			     143
#define CV186X_CLK_GPIO_DB		     144
#define CV186X_CLK_WGN			     145
#define CV186X_CLK_KEYSCAN		     146
#define CV186X_CLK_APB_EFUSE		     147
#define CV186X_CLK_EFUSE		     148
#define CV186X_CLK_INTC		     149
#define CV186X_CLK_OTP_C		     150
#define CV186X_CLK_100M		     151
#define CV186X_CLK_PWM			     152
#define CV186X_CLK_RTC_32K		     153
#define CV186X_CLK_XTAL_MISC		     154
#define CV186X_CLK_TEMPSEN		     155
#define CV186X_CLK_SARADC		     156
#define CV186X_CLK_100M_FREE		     157
#define CV186X_CLK_OTP			     158
#define CV186X_CLK_DBGSYS		     159
#define CV186X_CLK_AXI_VI		     160
#define CV186X_CLK_CSI_MAC0_VI		     161
#define CV186X_CLK_CSI_MAC1_VI		     162
#define CV186X_CLK_CSI_MAC2_VI		     163
#define CV186X_CLK_CSI_MAC3_VI		     164
#define CV186X_CLK_CSI_MAC4_VI		     165
#define CV186X_CLK_CSI_MAC5_VI		     166
#define CV186X_CLK_CSI_MAC6_VI		     167
#define CV186X_CLK_CSI_MAC7_VI		     168
#define CV186X_CLK_CSI_BE_VI		     169
#define CV186X_CLK_ISP_TOP_VI		     170
#define CV186X_CLK_RAW_VI		     171
#define CV186X_CLK_VPSS0_VI		     172
#define CV186X_CLK_VPSS1_VI		     173
#define CV186X_CLK_VPSS2_VI		     174
#define CV186X_CLK_VPSS3_VI		     175
#define CV186X_CLK_DWA0_VI		     176
#define CV186X_CLK_DWA1_VI		     177
#define CV186X_CLK_LDC0_VI		     178
#define CV186X_CLK_LDC1_VI		     179
#define CV186X_CLK_DPU_VI		     180
#define CV186X_CLK_IVE0_VI		     181
#define CV186X_CLK_IVE1_VI		     182
#define CV186X_CLK_STITCHING_VI	     183
#define CV186X_CLK_LVDS0_VI		     184
#define CV186X_CLK_LVDS1_VI		     185
#define CV186X_CLK_LVDS2_VI		     186
#define CV186X_CLK_LVDS3_VI		     187
#define CV186X_CLK_LVDS4_VI		     188
#define CV186X_CLK_LVDS5_VI		     189
#define CV186X_CLK_CSI0_RX_VI		     190
#define CV186X_CLK_CSI1_RX_VI		     191
#define CV186X_CLK_CSI2_RX_VI		     192
#define CV186X_CLK_CSI3_RX_VI		     193
#define CV186X_CLK_CSI4_RX_VI		     194
#define CV186X_CLK_CSI5_RX_VI		     195
#define CV186X_PAD_VI0_CLK0_VI		     196
#define CV186X_PAD_VI0_CLK1_VI		     197
#define CV186X_PAD_VI1_CLK_VI		     198
#define CV186X_PAD_VI2_CLK_VI		     199
#define CV186X_VD0_CLK_APB_VDSYS_TOP	     200
#define CV186X_VD0_CLK_APB_VDSYS_VD	     201
#define CV186X_VD0_CLK_APB_VDSYS_VPSS_0     202
#define CV186X_VD0_CLK_APB_VDSYS_VPSS_1     203
#define CV186X_VD0_CLK_VDSYS_VD	     204
#define CV186X_VD0_CLK_VDSYS_VPSS_0	     205
#define CV186X_VD0_CLK_VDSYS_VPSS_1	     206
#define CV186X_VD1_CLK_APB_VDSYS_TOP	     207
#define CV186X_VD1_CLK_APB_VDSYS_VD	     208
#define CV186X_VD1_CLK_APB_VDSYS_VPSS_0     209
#define CV186X_VD1_CLK_APB_VDSYS_VPSS_1     210
#define CV186X_VD1_CLK_VDSYS_VD	     211
#define CV186X_VD1_CLK_VDSYS_VPSS_0	     212
#define CV186X_VD1_CLK_VDSYS_VPSS_1	     213
#define CV186X_CLK_APB_VESYS_TOP	     214
#define CV186X_CLK_APB_VESYS_VE	     215
#define CV186X_CLK_APB_VESYS_JPEG_0	     216
#define CV186X_CLK_APB_VESYS_JPEG_1	     217
#define CV186X_CLK_APB_VESYS_JPEG_2	     218
#define CV186X_CLK_APB_VESYS_JPEG_3	     219
#define CV186X_CLK_VESYS_VE		     220
#define CV186X_CLK_VESYS_JPEG_0	     221
#define CV186X_CLK_VESYS_JPEG_1	     222
#define CV186X_CLK_VESYS_JPEG_2	     223
#define CV186X_CLK_VESYS_JPEG_3	     224
#define CV186X_VO_CLK_AXI		     225
#define CV186X_VO_CLK_2DE0		     226
#define CV186X_VO_CLK_2DE1		     227
#define CV186X_VO_CLK_OENC0		     228
#define CV186X_VO_CLK_OENC1		     229
#define CV186X_VO_CLK_VPSS0		     230
#define CV186X_VO_CLK_VPSS1		     231
#define CV186X_VO_CLK_DISP0		     232
#define CV186X_VO_CLK_DISP1		     233
#define CV186X_VO_CLK_VO_MAC0		     234
#define CV186X_VO_CLK_VO_MAC1		     235
#define CV186X_VO_CLK_DSI_MAC0		     236
#define CV186X_VO_CLK_DSI_MAC1		     237
#define CV186X_PCIEX2_CLK		     238
#define CV186X_PCIEX4_CLK		     239
#define CV186X_SATA_CLK		     240
#define CV186X_CLK_AHB_ROM		     241
#define CV186X_CLK_AXI4_EMMC		     242
#define CV186X_CLK_AXI4_SD0		     243
#define CV186X_CLK_AXI4_SD1		     244
#define CV186X_CLK_AXI4_ETH0		     245
#define CV186X_CLK_AXI4_ETH1		     246
#define CV186X_CLK_AHB_SF		     247
#define CV186X_CLK_SDMA0_AXI		     248
#define CV186X_CLK_SDMA1_AXI		     249
#define CV186X_CLK_SPI0		     250
#define CV186X_CLK_SPI1		     251
#define CV186X_CLK_SPI2		     252
#define CV186X_CLK_SPI3		     253
#define CV186X_CLK_APB_SPI0		     254
#define CV186X_CLK_APB_SPI1		     255
#define CV186X_CLK_APB_SPI2		     256
#define CV186X_CLK_APB_SPI3		     257
#define CV186X_CLK_APB_UART0		     258
#define CV186X_CLK_APB_UART1		     259
#define CV186X_CLK_APB_UART2		     260
#define CV186X_CLK_APB_UART3		     261
#define CV186X_CLK_APB_UART4		     262
#define CV186X_CLK_APB_UART5		     263
#define CV186X_CLK_APB_UART6		     264
#define CV186X_CLK_APB_UART7		     265
#define CV186X_CLK_APB_I2S_GLOBAL	     266
#define CV186X_CLK_APB_I2S0		     267
#define CV186X_CLK_APB_I2S1		     268
#define CV186X_CLK_APB_I2S2		     269
#define CV186X_CLK_APB_I2S3		     270
#define CV186X_CLK_APB_I2S4		     271
#define CV186X_CLK_APB_I2S5		     272
#define CV186X_CLK_APB_I2S6		     273
#define CV186X_CLK_I2C0		     274
#define CV186X_CLK_I2C1		     275
#define CV186X_CLK_I2C2		     276
#define CV186X_CLK_I2C3		     277
#define CV186X_CLK_I2C4		     278
#define CV186X_CLK_I2C5		     279
#define CV186X_CLK_I2C6		     280
#define CV186X_CLK_I2C7		     281
#define CV186X_CLK_I2C8		     282
#define CV186X_CLK_I2C9		     283
#define CV186X_CLK_APB_I2C0		     284
#define CV186X_CLK_APB_I2C1		     285
#define CV186X_CLK_APB_I2C2		     286
#define CV186X_CLK_APB_I2C3		     287
#define CV186X_CLK_APB_I2C4		     288
#define CV186X_CLK_APB_I2C5		     289
#define CV186X_CLK_APB_I2C6		     290
#define CV186X_CLK_APB_I2C7		     291
#define CV186X_CLK_APB_I2C8		     292
#define CV186X_CLK_APB_I2C9		     293
#define CV186X_CLK_CAN0		     294
#define CV186X_CLK_CAN1		     295
#define CV186X_CLK_APB_CAN0		     296
#define CV186X_CLK_APB_CAN1		     297
#define CV186X_CLK_APB_WDT		     298
#define CV186X_CLK_APB_MAILBOX		     299
#define CV186X_CLK_APB_OTP		     300
#define CV186X_CLK_APB_OTP_C		     301
#define CV186X_CLK_APB_GPIO		     302
#define CV186X_CLK_WGN0		     303
#define CV186X_CLK_WGN1		     304
#define CV186X_CLK_TIMER0		     305
#define CV186X_CLK_TIMER1		     306
#define CV186X_CLK_TIMER2		     307
#define CV186X_CLK_TIMER3		     308
#define CV186X_CLK_TIMER4		     309
#define CV186X_CLK_TIMER5		     310
#define CV186X_CLK_TIMER6		     311
#define CV186X_CLK_TIMER7		     312
#define CV186X_CLK_DUMMY_0		     313
#define CV186X_CLK_DUMMY_1		     314
#define CV186X_CLK_DUMMY_2		     315
#define CV186X_CLK_DUMMY_3		     316
#define CV186X_VO_CLK_HDMI_MAC		     317

#endif /* __DT_BINDINGS_CLK_CV186X_H__ */
